The development of Very Large Scale Integration (VLSI) is evolving along the line of a large wafer size and a small line width. This trend of development enhances the function of integrated circuits and reduces manufacturing costs. As the dimensions of semiconductor devices, such as complementary metal-oxide semiconductor (CMOS) transistors, are reduced, the channel length diminishes correspondingly to increase the operating speed of the transistor. As the dimensions of CMOS transistors are scaled down to 0.1 μm and below, in order to achieve continued improvements in integrated circuit density and performance, a significant number of new technological issues emerge. One of these is the scaling of the junctions. The junction depth xj needs to be scaled down in order to control the Short Channel Effect and Drain Induced Barrier Lowering, which may be detrimental to good transistor switching behavior.
Conventionally, the junctions are formed by impurity implantation and subsequent annealing. However, as the total number of activated atoms is limited by the solubility curve, a decrease of the junction depth automatically increases the access resistance Rj of the transistor. Moreover, it is very difficult to achieve well-defined and abrupt junctions by the process described above, due to scattering events during implantation and diffusion during activation. A way to overcome this Rs/xj trade-off is to manufacture metallic Schottky junctions, which present a far lower resistivity. Conventionally, such junctions is achieved by a silicidation process because of its selectivity.
Referring to FIG. 9a of the drawings, in a prior art metal-oxide semiconductor device fabrication process, a gate 140 is formed over a gate oxide layer 120 on a substrate 100. Next, an ion implantation step is performed in respect of the substrate 100 to form lightly doped drain (LDD) regions 110, as illustrated schematically in FIG. 9b of the drawings. A spacer 160 is formed on the sidewall of the gate 140, as shown in FIG. 9c, and a source/drain (S/D) implantation process is performed to form a source/drain region 130 in the substrate 100, as shown in FIG. 9d. Finally, following the subjection of the silicon wafer to a thermal process (such as annealing) to repair the crystal structure and drive in the dopants, silicide contacts 170 (or junctions) are formed on the source, drain and gate regions of the device by means of a silicidation step, to create a structure as illustrated schematically in FIG. 9e of the drawings.
In order to use the full potential of a metal Schottky junction, the control of the shape of the junction and of its position relative to the gate-controlled channel is of extreme importance. However, if a conventional silicidation process is used to form the junction, unwanted diffusion phenomena into the substrate or under the gate can occur during the metal-silicon reaction, such that the shape and position of the resultant junction may be adversely affected. On the other hand, a metal deposition process has been considered for forming the junction, which may overcome the problems outlined above and also widen the choice of possible Schottky materials that might be used. However, in contrast to silicidation, metal deposition is not selective to silicon and it is therefore desirable to provide a method of forming such junctions using metal deposition without causing metal to be deposited on other parts of the transistor, such as the spacers or STI region, which would inevitably cause short circuits.
It is preferred to provide a method of fabricating a self-aligned metal junction in respect of a semiconductor device, using a metal deposition process, as opposed to the silicidation techniques proposed in the prior art, wherein at least some of the problems outlined above are addressed.